From d891771ba32677138a6b545277cd0838642f3aef Mon Sep 17 00:00:00 2001 From: Will Lin Date: Thu, 18 Jun 2026 11:31:31 +0000 Subject: [PATCH] =?UTF-8?q?[revert]=20v2:=20drop=20FastWan/VSA=20registry?= =?UTF-8?q?=20entries=20=E2=80=94=20generic=20Wan=20loader=20can't=20map?= =?UTF-8?q?=20their=20gated-attn=20params?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit GPU verification (Wan2.1-Fun... no: FastWan2.1-T2V-1.3B) failed at load: 'Parameter blocks.0.to_gate_compress.bias not found in custom model state dict' — the FastVideo/* DMD-distilled checkpoints carry gated-attention params (to_gate_compress) that the generic WanTransformer3DModel loader can't map. v2/registry.py's select_by_architecture ALREADY rejects WanDMDPipeline for exactly this reason; my explicit ModelEntry wrongly bypassed it. Reverted FastWan (1.3B + 14B-480P) and the unverified VSA-14B alias (same FastVideo/* risk). Kept the official Wan2.1-T2V-14B (standard weights, same loader path as the GPU-verified 1.3B). Lesson recorded in V2_PORTING_STATUS.md: FastWan/Turbo/VSA need a param-mapping fix (like LTX-2.3 did), not just a schedule — bucket-C-effort. GPU-verify every port before claiming support. CPU mini 211/2. --- examples/inference/basic/V2_PORTING_STATUS.md | 6 ++++++ v2/registry.py | 3 +-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/examples/inference/basic/V2_PORTING_STATUS.md b/examples/inference/basic/V2_PORTING_STATUS.md index fde29f011..e58eecee6 100644 --- a/examples/inference/basic/V2_PORTING_STATUS.md +++ b/examples/inference/basic/V2_PORTING_STATUS.md @@ -57,6 +57,12 @@ Wan2.1 model — covered by wan21; those runtime modes are out of scope. ## Backlog — goal: port ALL fastvideo models (63 total: 8 ported · 21 reuse-arch · 34 new-arch) Ported (8): the 7 above + **Wan2.1-T2V-14B** (bucket B — reuses the Wan recipe/adapter; 720p defaults). +⚠️ Not as trivial as the bucket split implies: the `FastVideo/*` distilled checkpoints (FastWan DMD, VSA, +Turbo) carry **gated-attention params** (`to_gate_compress`) the generic `WanTransformer3DModel` loader +can't map (`select_by_architecture` already rejects `WanDMDPipeline` for this) — they need a param-mapping +fix (as LTX-2.3 did) on top of the few-step schedule, so they're really bucket-C-effort. GPU-verify each +port before claiming support. + **Bucket B (21 left) — reuse a v2 architecture** (`WanTransformer3DModel` / `CausalWanTransformer3DModel` / `LTX2Transformer3DModel`): a `ModelEntry` in `v2/registry.py` + a recipe (parameterize the wan21/wan_causal/ ltx2 builders) + `SamplingDefaults`, NO new adapter. Includes other Wan T2V sizes; i2v variants (need an diff --git a/v2/registry.py b/v2/registry.py index a937ebf0b..a5d88cbd5 100644 --- a/v2/registry.py +++ b/v2/registry.py @@ -53,8 +53,7 @@ def _entries() -> list[ModelEntry]: ) return [ ModelEntry(("Wan-AI/Wan2.1-T2V-1.3B-Diffusers",), build_wan21_card, build_wan_t2v_program), - ModelEntry(("Wan-AI/Wan2.1-T2V-14B-Diffusers", "FastVideo/Wan2.1-VSA-T2V-14B-720P-Diffusers"), - build_wan_t2v_14b_card, build_wan_t2v_program), + ModelEntry(("Wan-AI/Wan2.1-T2V-14B-Diffusers",), build_wan_t2v_14b_card, build_wan_t2v_program), ModelEntry(("Wan-AI/Wan2.2-TI2V-5B-Diffusers",), build_wan22_ti2v_card, build_wan_t2v_program), ModelEntry(("Wan-AI/Wan2.2-T2V-A14B-Diffusers",), build_wan22_a14b_card, build_wan_t2v_program), ModelEntry(("wlsaidhi/SFWan2.1-T2V-1.3B-Diffusers",), build_wan_causal_card, build_wan_causal_program),