 rlsu9
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f8089afbf1
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ema
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2024-11-30 02:44:36 +04:00 |
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rlsu9
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79e7dac0ac
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ok
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2024-11-29 21:50:49 +04:00 |
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rlsu9
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ed1e17f37f
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add ema transformer
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2024-11-29 11:42:17 +04:00 |
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Zhang Peiyuan
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6dd7980ec2
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[Feat] Refactor GAN; State saving & Resume; Experiments script (#59)
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2024-11-28 21:09:31 -08:00 |
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Zhang Peiyuan
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333488ac09
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[Feat][Debug] linear quadratic distill; HF precision bug (#56)
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2024-11-27 15:13:20 -08:00 |
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Zhang Peiyuan
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c7526707cc
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[Fix] Squeeze bug (#55)
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2024-11-26 13:29:03 -08:00 |
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Zhang Peiyuan
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a0ffbe2927
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[Feat] PCM Distill; Refactor FM logit to be compatible with all SD3/Flux scheduler. (#54)
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2024-11-26 12:26:24 -08:00 |
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Zhang Peiyuan
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897afb8b94
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Add LADD (#45)
Co-authored-by: Peiyuan Zhang <a1286225768@gmail.com>
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2024-11-15 19:28:41 -08:00 |
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f8178a5a14
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add lr scheduler; precision bug fix; add naive dataloader resume (#49)
Co-authored-by: Peiyuan Zhang <a1286225768@gmail.com>
Co-authored-by: Yongqi Chen <yongqich@gl1712.arc-ts.umich.edu>
Co-authored-by: Yongqi Chen <yongqich@gl-login3.arc-ts.umich.edu>
Co-authored-by: Yongqi Chen <yongqich@gl-login1.arc-ts.umich.edu>
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2024-11-14 19:57:38 -08:00 |
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4c76b3cc7a
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[Feat] Lora resume (#48)
Co-authored-by: Peiyuan Zhang <a1286225768@gmail.com>
Co-authored-by: Yongqi Chen <yongqich@gl1712.arc-ts.umich.edu>
Co-authored-by: Yongqi Chen <yongqich@gl-login3.arc-ts.umich.edu>
Co-authored-by: Yongqi Chen <yongqich@gl-login1.arc-ts.umich.edu>
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2024-11-12 22:30:58 -08:00 |
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3e0e8cf534
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Add lora (#47)
Co-authored-by: Yongqi Chen <144848849+BrianChen1129@users.noreply.github.com>
Co-authored-by: Yongqi Chen <yongqich@gl1712.arc-ts.umich.edu>
Co-authored-by: Yongqi Chen <yongqich@gl-login3.arc-ts.umich.edu>
Co-authored-by: Yongqi Chen <yongqich@gl-login1.arc-ts.umich.edu>
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2024-11-11 13:12:14 -08:00 |
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Zhang Peiyuan
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635fb2350d
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[Refactor] Switch to FSDP (#42)
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2024-11-09 15:46:25 -08:00 |
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Zhang Peiyuan
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e56b2ae0c4
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Add validation logging with SP (#36)
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2024-11-05 14:46:20 -08:00 |
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Zhang Peiyuan
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6c6d4b34e7
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[Feat] Sequence Parallel (#31)
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2024-11-05 08:13:01 -08:00 |
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rlsu9
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fd80dc653d
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switch to deepspeed dummyoptim
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2024-11-01 20:41:05 +04:00 |
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rlsu9
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97f48ef433
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Merge branch 'hl/diffusers' of https://github.com/jzhang38/FastVideo-OSP into peiyuan
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2024-11-01 04:44:23 +04:00 |
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rlsu9
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5975deed62
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OK
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2024-11-01 04:26:21 +04:00 |
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rlsu9
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60c420731d
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Add zero3
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2024-10-31 23:42:49 +04:00 |
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rlsu9
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a9a66a22a0
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Debug successful!
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2024-10-31 23:20:46 +04:00 |
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rlsu9
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5209b6ebdd
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debugging ..
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2024-10-30 21:25:48 +04:00 |
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a1286225768@gmail.com
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9e2c9eaa01
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overfitting ....
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2024-10-30 04:14:04 +00:00 |
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Peiyuan Zhang
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567f9f66f8
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debug
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2024-10-29 21:10:50 +00:00 |
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foreverpiano
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70f3407032
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update optimizer
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2024-10-29 12:42:04 +00:00 |
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Peiyuan Zhang
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d22d40c74a
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14
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2024-10-29 03:47:08 +00:00 |
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Peiyuan Zhang
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6fe5521667
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Update generate_synthetic.sh and deepspeed_zero2_config.yaml
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2024-10-29 01:00:31 +00:00 |
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Peiyuan Zhang
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d4e071be20
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training
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2024-10-29 00:38:40 +00:00 |
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Peiyuan Zhang
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7455bc9e7f
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commit first
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2024-10-28 23:39:15 +00:00 |
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Peiyuan Zhang
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45c89c46c5
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commit first
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2024-10-28 21:46:01 +00:00 |
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Peiyuan Zhang
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7ec6f8f720
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Deleted unnecessary files
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2024-10-28 19:21:00 +00:00 |
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Peiyuan Zhang
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8824f74609
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clean up name changing
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2024-10-28 17:54:38 +00:00 |
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Peiyuan Zhang
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f245e4b4f8
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Add mochi download & Change output dir
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2024-10-26 18:08:50 +00:00 |
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Peiyuan Zhang
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ea372da285
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Remove unused adaptor files
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2024-10-26 17:59:04 +00:00 |
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Peiyuan Zhang
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b6b1a2aa92
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Update T5Base
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2024-10-26 17:53:51 +00:00 |
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Peiyuan Zhang
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84cf3b6795
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Update t2v_debug_multi.sh with video_length_tolerance_range and dataloader_num_workers
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2024-10-25 09:58:41 +00:00 |
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Peiyuan Zhang
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182f4082f5
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Update max height and width for video processing
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2024-10-25 04:28:31 +00:00 |
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Peiyuan Zhang
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8d3f651217
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Add pretrained model for OpenSoraT2V-ROPE-L
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2024-10-25 04:26:57 +00:00 |
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Peiyuan Zhang
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15fbad6dd5
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Remove UDIT and inpaint
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2024-10-25 03:55:15 +00:00 |
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Peiyuan Zhang
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c00cc4b531
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Update PyTorch index URLs and video length tolerance range
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2024-10-25 03:18:16 +00:00 |
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