8 Commits

Include renames

Author	SHA1	Message	Date
Wenbo Ji　嵇文博	ef63de1f60	[perf] Fuse VSA64 tile layout for SM100 inference (#1900) ... For Wan VSA inference with 64-token tiles, each attention layer scattered Q, K, V and the gate into a tile buffer and then made four transposed copies. On SM100, one Triton kernel (tile_to_bhsd) now does the scatter and the transposes in one pass. Training, 256-token tiles, other GPUs and builds without the kernel use the previous path. FASTVIDEO_DISABLE_VSA64_FUSED_LAYOUT=1 turns the fused path off. On GB200 the layout and attention step goes from 15.7 ms to 8.6 ms. FastWan 1.3B frames are bit-exact with the previous path at sequence parallel 1 and 2.	2026-10-07 15:31:58 -07:00
3 people	72795d0af8	[perf] avoid full-sequence materialization in VSA coarse/sparse combine (#1813) ... Co-authored-by: Claude Opus 5 <noreply@anthropic.com> Co-authored-by: SolitaryThinker <wlsaidhi@gmail.com>	2026-10-07 01:54:35 -07:00
Yogya Mehrotra	a575055eec	[perf] benchmark_attn_qat_train: device peak-TFLOPS table instead of silent RTX 5090 default (#1724)	2026-09-24 17:08:03 -07:00
3 people	00338aa9ca	[perf] Add FA4 CuTe backward support for VSA-256 (#1639) ... Co-authored-by: Hyunsung Lee <hyunsungl@sizigistudios.com> Co-authored-by: alexzms <3036648523@qq.com>	2026-08-19 11:46:49 -07:00
William Lin	9028953625	[misc] yapf pass under CI's interpreter (3.12) + pin hook language_version (#1702)	2026-08-08 22:24:17 -07:00
3 people	9709b7513b	[feat] Port NVFP4 QAT/QAD to modular train framework (#1619) ... Co-authored-by: Peiyuan Zhang <email> Co-authored-by: Peiyuan <a>	2026-07-18 15:01:09 -07:00
xsankandmergify[bot]	31b719ae49	[perf] optimize compress & topk kernel (#1421) ... Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>	2026-06-23 18:51:22 +00:00
alexzms	dbf3917bf4	[fastvideo-kernel] replace map to index with Triton implementation + add vsa benchmark (#1029)	2026-01-22 11:35:02 -08:00