Extend the training-side regional-compile port (internal 863e87342, GO
verdict vsa_gate/compile_ab/VERDICT.md) to inference so every H3 run can
compile the 52 transformer blocks. Opt-in and off by default:
- New FastVideoArgs.inference_torch_compile (CLI --inference-torch-compile),
env FASTVIDEO_INFERENCE_TORCH_COMPILE=1 folded in __post_init__ (the
attention_backend parse-once pattern), reachable through
PipelineSelection.experimental {"inference_torch_compile": true} exactly
like the VSA_sparsity / VSA_tile_size knobs.
- maybe_load_fsdp_model applies the compile right after the transformer
loads: per-_compile_conditions block, fullgraph=True + inductor
options.emulate_precision_casts injected, no user kwargs needed (the
compile-A/B verdict recipe). prepare_for_compile still runs first, so the
H3 fusion-inertness warning of #1735 is preserved.
- _regional_compile_unsupported_reason ported from the training loader:
VSA / VSA-H3 backends and the FASTVIDEO_DISABLE_ATTENTION_COMPILE=1
escape hatch degrade the transformer to eager with one warning; FLASH_ATTN
on flash-attn 3 is rejected with an actionable message. FA4/FA2/SDPA
compile through their existing custom-op boundaries (forward-only is
enough at inference; the training port's backward custom ops are not
needed under no_grad).
- FASTVIDEO_DISABLE_ATTENTION_COMPILE default flipped to 0 (attention is
traced by default), matching the training port and upstream #1718 —
eager runs are unaffected (torch.compiler.disable is inert outside
dynamo).
- enable_torch_compile + inference_torch_compile together skip the
pipeline-level DiT compile (the loader already owns those forwards).
- examples: --inference-torch-compile on basic_minimax_h3_t2v.py (dense
target) and basic_fasth3.py (exercises the VSA degrade path).
- CPU-safe contract tests for the guard and the kwargs injection.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
MiniMaxH3Scheduler.set_timesteps(N) builds an N-point sigma grid ending at
0 and runs N-1 transformer forwards (the base model's '50 steps' preset is
49 forwards). The student was distilled on a 4-FORWARD grid
(t = 1000/750/500/250 -> 0 on the shift-12 schedule), so --steps 4 was
silently running a 3-forward, off-distribution grid. Default is now 5
grid points = the distilled 4-forward grid, with the convention documented
on the flag.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
FASTVIDEO_VSA_SM100A=1 (default off) sends no-grad tile-64 forwards through
fastvideo_kernel.block_sparse_attn_sm100a (the Blackwell block-sparse
forward merged in #1719, which handles per-q-tile NON-uniform q2k_num rows
and zero-count rows). Route preconditions: module importable,
is_supported() (sm_100 device, bf16, head_dim 128, even tile count), no
grad tracking; any failure with the env set logs one warning and falls
back to the Triton-64 kernels, which also keep the entire grad path
unchanged.
The bool block map is compacted with the same map_to_index the Triton bool
entry uses, so the sm_100a kernel sees H3's true NON-uniform per-row counts
(prefix query tiles dense, video tiles prefix+top-k).
The FastH3 example surfaces the route as --vsa-kernel {triton,sm100a}
(default triton), which sets the env before pipeline boot so spawned GPU
workers inherit it; documented in the basic README.
CPU route-selection tests: default-off, engage-on-env, grad fallback,
warn-once fallback for missing module/unsupported geometry, no-grad-context
detection.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
