 Eric LiangandEricLiang
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e028dcc7c0
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[Backend][Vmoba] Add implementation of VMoba (#778)
Co-authored-by: EricLiang <https://github.com/EricLina>
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2025-09-08 23:53:25 -07:00 |
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Wenxuan Tanandgemini-code-assist[bot]
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076f45c1ee
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[Feature] Support Lora for DMD (#755)
Co-authored-by: gemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
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2025-09-08 14:18:21 -07:00 |
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Wei ZhouandSolitaryThinker
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ce67cd3729
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[Feat] Support Self-Forcing's Causal Inference for Wan2.1 T2V 1.3B (#766)
Co-authored-by: SolitaryThinker <wlsaidhi@gmail.com>
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2025-08-28 16:47:49 -07:00 |
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Peng Xiaoand肖鹏
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a0bff12746
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[bugfix] [dmd] Align backward simulation with dmd2 sample back (#744)
Co-authored-by: 肖鹏 <xiaopeng1@aishi.ai>
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2025-08-20 22:25:33 -07:00 |
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William Lin
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6ceb4942a0
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[bugfix] [dmd] Fix backward simulation and also naming in wan_i2v_dmd_pipeline (#731)
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2025-08-10 21:13:30 -07:00 |
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William Lin
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2a773fa34e
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[bugfix] [distill] remove i2v validation schema import in distill (#728)
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2025-08-09 20:47:42 -07:00 |
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Wenxuan Tan
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5357f63327
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Fix LoRA load from training checkpoint (#719)
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2025-08-09 20:46:00 -05:00 |
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Wenxuan Tan
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6c6bcd914d
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Remove all empty_cache (#713)
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2025-08-07 22:50:38 -07:00 |
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Jinzhe Pan
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f2bc037fff
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[Fix] training pipeline pin_cpu_memory issue (#692)
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2025-08-07 02:31:20 -07:00 |
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Wei ZhouandSolitaryThinker
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c41305ad18
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[Feat] Add Wan2.2 14B MoE (#688)
Co-authored-by: SolitaryThinker <wlsaidhi@gmail.com>
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2025-08-06 20:31:03 -07:00 |
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Yongqi ChenandSolitaryThinker
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b65f0316d1
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[Feature] Add Wan2.2 DMD example files; Update lr scheduler (#694)
Co-authored-by: SolitaryThinker <wlsaidhi@gmail.com>
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2025-08-03 22:55:01 -04:00 |
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Yongqi ChenandSolitaryThinker
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5f42748ed1
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[Feature] Add Wan2.2-TI2V-5B Sparse Distill (#690)
Co-authored-by: SolitaryThinker <wlsaidhi@gmail.com>
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2025-08-03 01:29:57 -04:00 |
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Yongqi Chen
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dfe0b288e1
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[Bugfix] Add i2v vae loading (#686)
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2025-08-01 23:15:37 -04:00 |
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Yongqi Chen
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9185978c55
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[Bugfix] Fix multi-gpu training lr_scheduler (#682)
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2025-08-01 15:54:03 -04:00 |
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MartinPernus
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fcba463553
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[Bugfix] fix _normalize_dit_input (#681)
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2025-08-01 05:10:27 -04:00 |
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Yongqi Chen
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2c53d3eecf
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[Feature]Add DMD visualization for debugging (#674)
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2025-07-31 05:54:47 -04:00 |
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Yongqi Chen
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a113311e77
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[Bugfix][Training]Fix Wan2.2 training vae config issue (#668)
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2025-07-30 12:24:45 -07:00 |
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Yongqi Chen
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f759980a58
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[Feature]Add VSA slurm training example scripts (#666)
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2025-07-30 01:27:54 -04:00 |
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Zhang Peiyuan
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37e0f8c236
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[BUG] Fix distillation + vsa (#665)
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2025-07-29 19:48:11 -07:00 |
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Kevin Lin
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51711d5906
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[ComfyUI] Add __init__.py for node discovery (#663)
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2025-07-29 18:21:09 -07:00 |
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William LinandJerryZhou54
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6375223b16
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[Feature] Add wan2.2 5B T2V (#658)
Co-authored-by: JerryZhou54 <zhouw.jerry2017@outlook.com>
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2025-07-29 17:16:03 -07:00 |
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Yongqi Chen
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4cb046768d
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[Feature]Add DMD distillation training resume checkpoint; Update DMD CI test (#662)
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2025-07-29 19:06:05 -04:00 |
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Yongqi Chen
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3322542444
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[Feature] Add DMD CI test (#661)
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2025-07-29 03:14:00 -04:00 |
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Yongqi Chen
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65f707354b
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[Bugfix]Fix mdoel inference checkpoint saving when enabling HSDP (#660)
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2025-07-28 22:39:06 -07:00 |
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Yongqi Chen
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109e2e7e9d
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[Bugfix]Fix DMD wan pipeline (#659)
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2025-07-28 21:50:44 -07:00 |
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Zhang Peiyuan
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cbc3a6bb9d
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[Feat] Support VSA with any resolution. (#650)
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2025-07-28 20:14:40 -07:00 |
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Jinzhe Pan
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7b6c8aee99
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[2/3][Preprocess] refactor pipeline registry & file structure (#639)
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2025-07-27 23:30:17 -07:00 |
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Yongqi Chen
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202b2f3972
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[Feature] Ignore [union-attr] and [override] mypy check and remove from training (#652)
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2025-07-27 04:34:38 -04:00 |
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Yongqi Chen
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247fe273d8
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[Feature] Add DMD T2V training pipeline (#651)
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2025-07-27 03:35:51 -04:00 |
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William Lin
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81c9df629c
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[core] Add offloading for vae and image encoder and rename offloading args (#643)
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2025-07-25 17:55:03 -07:00 |
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William Lin
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f572319bd9
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[Feature] Remove V1 folder (#642)
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2025-07-24 22:43:12 -07:00 |
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