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will/kv_cache_fix_rebased
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41 Commits
Author SHA1 Message Date
RandNMR73 eddc7efc64 inference works after changes added 
new branch

Stop backprop through kv_cache

Enable timestep warping & using SelfForcing scheduler

checkpoint

text preprocessing ready

fix rotary embedding

Change Wan DiT to have 0 numerical diff with SF's Wan
 2025-09-22 02:29:16 +00:00
Wei ZhouRandNMR73SolitaryThinker
 		31f000d1cc [self-forcing] [5/n] Add Self-Forcing distillation pipeline (#808) 
Co-authored-by: RandNMR73 <notomatthew31@gmail.com>
Co-authored-by: SolitaryThinker <wlsaidhi@gmail.com>
 2025-09-20 19:32:10 -07:00
William Lin c5f9ea53b2 [self-forcing] [4/n] Preprocessing for collecting ODE trajectory (#788) 2025-09-15 17:54:42 -07:00
William LinandRandNMR73 ac11127397 [Self-forcing] [1/n] Handle extra dim in time embedding and add timestep warping (#792) 
Co-authored-by: RandNMR73 <notomatthew31@gmail.com>
 2025-09-09 02:52:02 -07:00
Wei ZhouandSolitaryThinker 359151d9a0 [Feature] Add wan2.2 5b i2v (#760) 
Co-authored-by: SolitaryThinker <wlsaidhi@gmail.com>
 2025-08-28 18:15:59 -07:00
Wei ZhouandSolitaryThinker ce67cd3729 [Feat] Support Self-Forcing's Causal Inference for Wan2.1 T2V 1.3B (#766) 
Co-authored-by: SolitaryThinker <wlsaidhi@gmail.com>
 2025-08-28 16:47:49 -07:00
Wenxuan Tan 5357f63327 Fix LoRA load from training checkpoint (#719) 2025-08-09 20:46:00 -05:00
Jinzhe Pan f2bc037fff [Fix] training pipeline pin_cpu_memory issue (#692) 2025-08-07 02:31:20 -07:00
Wei ZhouandSolitaryThinker c41305ad18 [Feat] Add Wan2.2 14B MoE (#688) 
Co-authored-by: SolitaryThinker <wlsaidhi@gmail.com>
 2025-08-06 20:31:03 -07:00
Wenxuan Tan 6c81befc87 [Feature] Optionally enable torch compile (#684) 2025-08-01 20:17:40 -07:00
William LinandJerryZhou54 6375223b16 [Feature] Add wan2.2 5B T2V (#658) 
Co-authored-by: JerryZhou54 <zhouw.jerry2017@outlook.com>
 2025-07-29 17:16:03 -07:00
Jinzhe Pan 7b6c8aee99 [2/3][Preprocess] refactor pipeline registry & file structure (#639) 2025-07-27 23:30:17 -07:00
Yongqi Chen 247fe273d8 [Feature] Add DMD T2V training pipeline (#651) 2025-07-27 03:35:51 -04:00
William Lin 81c9df629c [core] Add offloading for vae and image encoder and rename offloading args (#643) 2025-07-25 17:55:03 -07:00
William Lin f572319bd9 [Feature] Remove V1 folder (#642) 2025-07-24 22:43:12 -07:00
William Lin 576c214f28 [v0] Remove V0 code (#621) 2025-07-15 22:05:16 -07:00
eeecho d5ec468d43 [V0] [Distill] support distill in V0 for wan (#444) 2025-06-04 16:20:14 -07:00
applesaucethebunandBrayden Zhong 12647457a7 [Misc] Small fixes to Torch code (#395) 
Co-authored-by: Brayden Zhong <b8zhong@uwaterloo.ca>
 2025-05-23 14:40:24 -07:00
applesaucethebunandBrayden Zhong 51956369a5 [Misc] Replace instances of time.time() with time.perf_counter() (#396) 
Co-authored-by: Brayden Zhong <b8zhong@uwaterloo.ca>
 2025-05-11 15:56:39 -07:00
Yongqi ChenandPeiyuan Zhang d869d90d12 fix training mask strategy issue (#248) 
Co-authored-by: Peiyuan Zhang <a1286225768@gmail.com>
 2025-03-05 20:00:16 -08:00
Yongqi ChenandPeiyuan Zhang 0be4fc62c9 fix train/distill issue (#215) 
Co-authored-by: Peiyuan Zhang <a1286225768@gmail.com>
 2025-02-25 08:11:17 -08:00
Yongqi ChenandPeiyuan Zhang 1e08893546 Added multi-GPU support for Hunyuan STA (#211) 
Co-authored-by: Peiyuan Zhang <a1286225768@gmail.com>
 2025-02-21 14:16:28 -08:00
Zhang Peiyuan 59ec42f40e [FIX] Make STA optinal (#204) 2025-02-20 13:09:50 -08:00
rlsu9 5ae5b247b3 [FIX] fix isort format (#203) 2025-02-20 12:20:20 -08:00
Zhang Peiyuanrlsu9BrianChen1129
 		ead6c62be4 [Feat] Add STA for StepVideo (#200) 
Co-authored-by: rlsu9 <r3su@ucsd.edu>
Co-authored-by: BrianChen1129 <yongqich@umich.edu>
 2025-02-20 11:33:58 -08:00
Yongqi ChenandPeiyuan Zhang 6805eaa06c [bug]: fix ori hunyuan inference issue (#199) 
Co-authored-by: Peiyuan Zhang <a1286225768@gmail.com>
 2025-02-19 14:18:15 -08:00
rlsu9 a3ec969397 [feat]: fix readme demo and add video to readme (#191) 2025-02-18 17:46:32 -05:00
Yongqi ChenandPeiyuan Zhang 76a12cc8a1 Infer sta tea with torch.compile (#190) 
Co-authored-by: Peiyuan Zhang <a1286225768@gmail.com>
 2025-02-18 11:29:36 -08:00
Yongqi ChenandPeiyuan Zhang 9ea39cee57 Add STA and teacache forward (#184) 
Co-authored-by: Peiyuan Zhang <a1286225768@gmail.com>
 2025-02-15 16:22:01 -08:00
Brian Chen 218449c54d adding hunyuan hf (support lora finetuning); unified hunyuan hf inference with quantization (#135) 2025-01-13 19:47:42 -08:00
Yuzhou Nieand“Peiyuan Zhang” 4a1f1e35bb add parallel for vae decoding (#134) 
Co-authored-by: “Peiyuan Zhang” <a1286225768@gmail.com>
 2025-01-07 17:14:21 -08:00
rlsu9 0aed1868df [feat]: Add format auto fixer to main branch (#124) 2024-12-31 15:23:17 -08:00
Brian Chen edf116fa46 fix lora checkpoint saving issue (#97) 2024-12-19 08:42:59 -08:00
Zhang Peiyuanrlsu9rlsu9
 		a57122c519 Rlsu lora readme (#86) 
Co-authored-by: rlsu9 <r3su@ucsd.edu>
Co-authored-by: rlsu9 <147024991+rlsu9@users.noreply.github.com>
 2024-12-17 11:37:07 -08:00
Zhang Peiyuanandrlsu9 b393570e45 Update README (#85) 
Co-authored-by: rlsu9 <r3su@ucsd.edu>
 2024-12-16 17:06:14 -08:00
Zhang Peiyuanandrlsu9 58cfd71b5e Cleanup 
Co-authored-by: rlsu9 <r3su@ucsd.edu>
 2024-12-15 17:03:29 -08:00
Zhang Peiyuan 85639d1101 [feat] add hunyuan adv (#79) 2024-12-13 11:52:57 -08:00
Zhang Peiyuanandforeverpiano 6ab2263f3a [Feat] Add HunyuanVideo (#78) 
Co-authored-by: foreverpiano <pianoqwz@qq.com>
 2024-12-12 14:14:09 -08:00
Zhang Peiyuanandrlsu9 b421c2e183 Cleanup (#77) 
Co-authored-by: rlsu9 <r3su@ucsd.edu>
 2024-12-12 14:04:02 -08:00
Zhang Peiyuan de1e8d868e Cleanup (#75) 2024-12-06 20:56:06 -08:00
Zhang Peiyuanandforeverpiano 8d41d505fe [cleanup] (#72) 
Co-authored-by: foreverpiano <pianoqwz@gmail.com>
 2024-12-05 21:02:10 -08:00