root and Claude Fable 5.1
749a9c5d97
[kernel] sm_100a CUDA backward for VSA block-sparse attention (64-token blocks)
...
Native GB200 (sm_100a) backward pairing with the sm_100a forward: one
warp-specialized tcgen05 kernel per (batch, head, kv64 block) computing dK, dV
and the dQ partials (fp32 accumulator, cp.reduce.async.bulk), plus a preprocess
(Delta, Q^T, dO^T, dqaccum zero, exact-zero dK/dV rows for unselected kv
blocks) and a postprocess (dQ unscramble + sm_scale). Consumes the forward's
lse (Triton M format) and invert_indices' k2q metadata unchanged; returns
(dq, dk, dv) in bf16 with the Triton backward's scaling.
Wiring: with FASTVIDEO_VSA_SM100A=1 the autograd backward of the sm_100a
forward op runs this kernel when block_sparse_attn_bwd_sm100a.is_supported
passes (bf16, head_dim 128, 64-token blocks, even block count, sm_100a device,
op built) and the Triton backward otherwise. No new environment variable.
primitives.cuh gains only the backward's primitives (additions only; the
forward's definitions and SASS are untouched). Built for sm_100a only: the
kernel is validated on GB200, not yet on B300/GB300, so sm_103a devices keep
the Triton backward. The H3 backend's grad gate is unchanged (separate PR).
Semantics: per-row k2q counts may differ arbitrarily (one work item is one kv
row; count 0 is skipped identically by every warp and gets zero dK/dV rows);
variable_block_sizes masks padded kv rows per lane; is_supported reads no
tensor contents. Work-item order: a device kernel sorts by list length from
1024 kv blocks per sequence on; below that a cached identity array is passed.
Tests (GB200, extension built from this branch): tests/test_block_sparse_bwd_sm100a.py
15 passed (fp32 masked-dense autograd reference; ragged vbs, zero-count kv
blocks, top-k 1/2/3/5/7, batch 2), tests/test_block_sparse_sm100a_dispatch.py
10 passed (sm_100a route vs all-Triton grads, ragged vbs, Triton backward
monkeypatched to fail on a supported input), tests/test_block_sparse_sm100a.py
37 passed (forward regression).
Perf (kernels only, same window, B=1 H=8 D=128, 25% density, fp32 accumulator,
TFLOPS on selected blocks) Triton backward vs this kernel:
4k 198/381 (1.93x), 8k 313/575 (1.84x), 16k 389/715 (1.84x), 32k 433/794
(1.84x), 65k 448/821 (1.83x), 131k 452/736 (1.63x), 262k 452/784 (1.73x),
524k 437/771 (1.76x). FastVideo autograd path incl. invert_indices: 1.6-1.7x
at Wan 480P/720P-like shapes.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com >
2026-09-04 19:39:36 -07:00
SYLAR
7bb76b5ec9
[feat] Add native SM103a VSA support ( #1812 )
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Signed-off-by: lishunyang12 <lishunyang12@163.com >
2026-09-03 15:00:28 -07:00
Aryan Kumar and Aryan Kumar
0bd19a976b
[docs]: add one-Spark FastH3 cookbook runtime with a device-count row ( #1811 )
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Co-authored-by: Aryan Kumar <aryan5v@users.noreply.github.com >
2026-09-02 10:05:59 -07:00
Aryan Kumar and Aryan Kumar
cf6a00b9be
[feat]: add opt-in CUDA TAEH3 preview decode for FastH3 ( #1795 )
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Co-authored-by: Aryan Kumar <aryan5v@users.noreply.github.com >
2026-08-31 23:34:56 -07:00
Aryan Kumar and Aryan Kumar
26064193e2
[feat] Add an H3 server cookbook and prompt playground ( #1798 )
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Co-authored-by: Aryan Kumar <aryan5v@users.noreply.github.com >
2026-08-31 22:14:33 -07:00
ac48bb3cd1
[feat] Add MiniMax H3 MLX T2VA inference ( #1770 )
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Co-authored-by: Aryan Kumar <aryank@Aryans-Mac-Studio.local >
Co-authored-by: coderabbitai[bot] <136622811+coderabbitai[bot]@users.noreply.github.com>
Co-authored-by: CodeRabbit <noreply@coderabbit.ai >
2026-08-28 12:54:33 -07:00
KyleNeverGivesUp
c9c5585758
[perf]: MiniMax H3 on GB10 - skip text encoder CPU offload on unified memory (5m49s to 30ms) ( #1710 )
2026-08-26 12:03:14 -07:00
lpc0220
7a4285189f
[kernel] Route block-sparse VSA to the sm_100a forward behind FASTVIDEO_VSA_SM100A (opt-in) ( #1754 )
2026-08-24 15:26:56 -07:00
William Lin
f9e3680f11
[perf] Align FastH3 optimized inference profile ( #1748 )
2026-08-23 02:01:03 -07:00
Kaiqin Kong
bcffa4026e
[perf] Optimize MiniMax-H3 text encoder memory ( #1732 )
2026-08-21 14:57:06 -07:00
KyleNeverGivesUp
0462e1b0e7
[perf]: MiniMax H3 - build the Qwen3-VL encoder only as far as it is read (-13.7 GB) ( #1711 )
2026-08-20 23:19:25 -05:00
lpc0220
907f2100ec
[kernel] sm_100a CUDA block-sparse VSA forward (Blackwell), 64- and 128-token blocks ( #1719 )
2026-08-20 23:16:25 -05:00
Kaiqin Kong
e0a3db5651
[perf] Reduce MiniMax-H3 VAE peak memory ( #1703 )
2026-08-20 23:13:23 -05:00
Kai
0653f8f3af
[new-model] Add V2A: native MMAudio inference pipeline ( #1622 )
2026-08-09 17:29:27 -07:00
William Lin
9028953625
[misc] yapf pass under CI's interpreter (3.12) + pin hook language_version ( #1702 )
2026-08-08 22:24:17 -07:00
Kaiqin Kong
e8b0e4c61e
[feat] Add MiniMax H3 ( #1674 )
2026-08-04 13:54:39 -07:00
William Lin
af2934dd6b
[feat]: FA4-FP4 ATTN_QAT_INFER on sm_100/sm_103 + NVFP4 weight purge ( #1647 )
2026-07-27 15:46:52 -07:00
Junda Su
755a4e4470
[new-model] Add LingBot-Video Dense and MoE/refiner T2V inference ( #1595 )
2026-07-18 20:18:16 -07:00
Junda Su
d4bdd3621a
[new-model] Port LingBot-World-v2 ( #1579 )
2026-07-16 19:51:53 -07:00
6966f9e0bc
[fix] Z-Image ( #1236 ) draft port: rebase + strict-load contract + bf16 encoder parity + PORT_STATUS ( #1339 )
...
Co-authored-by: Mrinaal Dogra <mdogra@ucsd.edu >
Co-authored-by: SolitaryThinker <wlsaidhi@gmail.com >
2026-07-16 18:18:25 -07:00
b063f8ca41
[feat] Fix FLUX.1-dev port: native RoPE, parity tests, SSIM reference ( #1321 )
...
Co-authored-by: Ishan Vaish <ivaish@ucsd.edu >
Co-authored-by: Claude Opus 4.8 <noreply@anthropic.com >
2026-07-13 01:49:42 -07:00
Shreejith SG and H1yori233
d82abc271e
[feat] Add GLM-Image inference support ( #1030 )
...
Co-authored-by: H1yori233 <k1kong@ucsd.edu >
2026-07-12 22:42:42 -07:00
595f0ea60e
[feat] Add DreamX-World 5B Cam and AR pipelines ( #1538 )
...
Co-authored-by: Suckl <Suckl@users.noreply.github.com >
Co-authored-by: SolitaryThinker <wlsaidhi@gmail.com >
2026-07-07 06:16:18 +00:00
William Lin
9d909f5f04
[test]: remove dead and duplicate tests (-489 lines) ( #1556 )
2026-07-05 15:53:40 -07:00
Junda Su and Peiyuan Zhang
5854aec2ce
[feat] Add Wan RL DiffusionNFT training ( #1450 )
...
Co-authored-by: Peiyuan Zhang <a1286225768@gmail.com >
2026-06-11 21:18:59 -07:00
d922ab2cbc
[model] Flux2 Klein Port ( #1349 )
...
Co-authored-by: Gnav3852 <63612880+Gnav3852@users.noreply.github.com >
Co-authored-by: Mac Lee <macthecadillac@gmail.com >
2026-06-09 14:55:55 -07:00
e8597b7448
[Bugfix] FP4 FA4 installation fix ( #1367 )
...
Co-authored-by: Claude Opus 4.6 (1M context) <noreply@anthropic.com >
Co-authored-by: gemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Co-authored-by: SolitaryThinker <wlsaidhi@gmail.com >
2026-05-19 22:45:24 -07:00
William Lin
c5088670c8
[misc]: empty __init__.py files with no logic ( #1346 )
2026-05-13 13:09:40 -07:00
b4458e5bae
feat: FP4 Flash Attention 4 for Blackwell GPUs ( #1221 )
...
Co-authored-by: Claude Opus 4.6 (1M context) <noreply@anthropic.com >
Co-authored-by: gemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2026-05-12 17:04:39 -07:00
William Lin
b7a448cf5b
[feat]: MagiHuman pipeline orchestrator + 10-test parity battery (5/8) ( #1299 )
2026-05-12 15:12:54 -07:00
William Lin
de803cb250
[feat]: MagiHuman DiT (transformer) port + parity tests (3/8) ( #1297 )
2026-05-12 14:49:03 -07:00
William Lin
b1ddb1ba33
[feat]: T5-Gemma encoder for MagiHuman pipeline (2/8) ( #1296 )
2026-05-12 13:59:55 -07:00
William Lin and Raghav
e3a5c6954f
[misc]: import add-model skill stack to .agents/skills/ ( #1308 )
...
Co-authored-by: Raghav <ragg04@gmail.com >
2026-05-09 13:06:54 -07:00
William Lin
140bd1a6cf
[misc]: standardize install instructions on uv pip install ( #1279 )
2026-05-02 12:45:50 -07:00
William Lin
9801037c3d
[refactor] tests/local_tests: organize by model family ( #1269 )
2026-05-01 01:49:54 -07:00
William Lin
c77a76c6af
[feat] Stable Audio Open 1.0: T2A + A2A + RePaint inpainting (native) ( #1260 )
2026-05-01 00:07:11 -07:00
William Lin
70ee5d230c
[feat] [6/n] Improve API: LTX-2 public preset + asset wiring + gpu_pool translation ( #1239 )
2026-04-23 11:36:45 -07:00
William Lin
145a3f166b
[feat] [4/n] Improve API: refactor sampling param and merge with presets ( #1234 )
2026-04-16 14:10:02 -07:00
f6e65ff668
[Feature] Add BSA (Bidirectional Sparse Attention) inference backend ( #1174 )
...
Co-authored-by: Satyam Srivastava <satyam53@Mac.lan1 >
Co-authored-by: Satyam Srivastava <satyam53@Satyams-MacBook-Air.local >
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2026-04-05 05:00:33 +00:00
vishruthb
5789955bbe
[feat] add gen3c (cosmos-7b) model and pipeline support ( #1059 )
2026-04-01 11:42:02 +00:00
alexzms
b3edfacdd8
[bugfix]: fix I2V preprocessing crash for models without CLIP (Wan2.2 I2V) ( #1184 )
2026-03-28 10:28:50 +08:00
jaisurya27
4d49f7b0aa
Kandinsky5 lite dit clean ( #1088 )
2026-03-26 08:07:11 +08:00
Zhang Peiyuan
fea556269b
[Misc] Fix memory leakage in VideoGenerator ( #1132 )
2026-02-26 19:51:32 -08:00
Zhang Peiyuan
128d0b7fc5
[Misc] Remove Teacache ( #1121 )
2026-02-22 16:53:07 -08:00
8e39ce38c9
[Feat] Native dit implementation for SD3.5 ( #1093 )
...
Co-authored-by: Ishan Vaish <vaish.ishan@gmail.com >
Co-authored-by: Cursor <cursoragent@cursor.com >
2026-02-18 10:19:40 +08:00
Mihir Jagtap
7a83e0e6fc
[feature] Add Hunyuan-GameCraft model support ( #1071 )
2026-02-14 08:07:44 +08:00
Ishan and Jinzhe Pan
0aff68f51d
[Feat] Add Stable Diffusion 3.5 ( #1075 )
...
Co-authored-by: Jinzhe Pan <eigensystem1318@gmail.com >
2026-02-10 14:31:36 +08:00
ad58f802f3
[Feat] Port LTX2 trainer ( #1074 )
...
Co-authored-by: Davids048 <jundasu@ucsd.edu >
Co-authored-by: Matthew Noto <99706358+RandNMR73@users.noreply.github.com >
2026-02-09 17:32:57 -08:00
Shao Duan and Will Lin
029216029f
Added LTX-2 Distilled T2V Generation ( #1016 )
...
Co-authored-by: Will Lin <wlsaidhi@gmail.com >
2026-01-21 14:11:39 -08:00
Wenxuan Tan
7244a4b27f
[CI] Add LoRA inference tests ( #546 )
2025-07-15 15:06:44 -05:00
