William Lin
cdda1b7535
[feat] Add H3 PDD/DMPDD training and packed Ref2VA preprocessing ( #1984 )
2026-10-20 11:15:57 -07:00
lpc0220 and root
d4ed61cc7c
[refactor] VSA: rename the sm100a block-sparse kernel to ptx_blackwell ( #1956 )
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Co-authored-by: root <root@ptyche0124.ptyche.clusters.nvidia.com >
2026-10-17 21:10:19 -07:00
William Lin and Claude Opus 5.5
d1416b5930
[misc]: re-run pre-commit after the 2026-10-07 merges ( #1929 )
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Co-authored-by: Claude Opus 5.5 (1M context) <noreply@anthropic.com >
2026-10-07 06:13:43 -07:00
Zhang Peiyuan and Claude Opus 5.5
c520878fd2
[perf]: QAT/QAD add safe regional compile for modular training ( #1718 )
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Adds opt-in regional torch.compile to the YAML-driven modular Wan trainer (training.model.enable_torch_compile / torch_compile_kwargs) with FA4 and Wan modulation forward/backward as opaque custom ops, compiled repeated DiT blocks after FSDP setup, and activation checkpointing applied before FSDP for trainable Wan transformers.
Merged with main's #1716 (WanModel resolves the checkpointing type in __init__; the PR's pre-FSDP wrap uses it and the post-load wrap is gone) and #1757 (pre_fsdp_model_transform runs before this PR's pre_fsdp_transform). Maintainer review (Swarm order #776 ): AdaLN skip names are canonicalized through checkpoint-wrapper prefixes, test_inference_regional_compile.py joins the unit lane, the Wan modulation custom-op test moved to the transformer lane, regional_compile is classified in the schema inventory, and a 1/2-GPU training smoke covers fully_shard(CheckpointWrapper) in eager and regional-compile modes. Validated on GB200: the FA4 CuTe forward/backward parity and fullgraph-backward tests and all four smoke cases pass.
Also exempts MMAudio recipes, whose student builds its pipeline config at init, from the fine-tuning recipe construction check that #1648 left failing on main.
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com >
2026-10-07 05:24:24 -07:00
3467f8befb
[feat] Add end-to-end MMAudio V2A training, inference, and evaluation ( #1648 )
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Co-authored-by: SolitaryThinker <wlsaidhi@gmail.com >
Co-authored-by: Claude Opus 5.5 (1M context) <noreply@anthropic.com >
2026-10-07 04:25:00 -07:00
d5287f8352
[feat]: add MiniMax H3 Ref2VA and LoRA training support ( #1757 )
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Co-authored-by: William Lin <8941107+SolitaryThinker@users.noreply.github.com >
Co-authored-by: SolitaryThinker <wlsaidhi@gmail.com >
Co-authored-by: Claude Opus 5.5 (1M context) <noreply@anthropic.com >
2026-10-07 03:21:45 -07:00
6102fac00d
[bugfix]: fix modular ops activation checkpoint recomputation ( #1716 )
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Co-authored-by: William Lin <8941107+SolitaryThinker@users.noreply.github.com >
Co-authored-by: SolitaryThinker <wlsaidhi@gmail.com >
Co-authored-by: Claude Opus 5.5 (1M context) <noreply@anthropic.com >
2026-10-07 02:41:12 -07:00
1ad33c1832
[feat] Support training_cfg_rate > 0 for LTX-2 ( #1752 )
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Co-authored-by: SolitaryThinker <wlsaidhi@gmail.com >
Co-authored-by: Claude Opus 5.5 (1M context) <noreply@anthropic.com >
2026-10-07 02:38:42 -07:00
a4e7322ba6
[bugfix]: synchronize post-FSDP LoRA replicas ( #1666 )
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Co-authored-by: Suckl <Suckl@users.noreply.github.com >
Co-authored-by: SolitaryThinker <wlsaidhi@gmail.com >
Co-authored-by: Claude Opus 5.5 (1M context) <noreply@anthropic.com >
2026-10-07 01:53:30 -07:00
abe98e87f5
[feat] Add phase-aware modular training performance metrics ( #1826 )
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Co-authored-by: SolitaryThinker <wlsaidhi@gmail.com >
Co-authored-by: Claude Opus 5.5 (1M context) <noreply@anthropic.com >
2026-10-07 01:30:11 -07:00
William Lin
ffc1a7a58b
[refactor] H3 pipeline cleanup: shared helpers, dead machinery, loop-invariant hoists ( #1698 )
2026-08-09 04:51:31 -07:00
Junda Su
c3567eb468
[feat] add Minimax H3 sft pipeline ( #1688 )
2026-08-07 16:12:04 -07:00
William Lin
7b094c945b
[refactor]: resolve attention backend once per component at load time ( #1657 )
2026-08-02 15:07:42 -07:00
William Lin
bf18371afe
[feat] Enable LTX-2 NVFP4 linear and attention QAT fine-tuning ( #1626 )
2026-07-26 02:19:34 -07:00
9709b7513b
[feat] Port NVFP4 QAT/QAD to modular train framework ( #1619 )
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Co-authored-by: Peiyuan Zhang <email>
Co-authored-by: Peiyuan <a>
2026-07-18 15:01:09 -07:00
Mingjia Huo and Claude Fable 5
4c08ffce49
[feat] World model training using third person games ( #1443 )
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Co-authored-by: Claude Fable 5 <noreply@anthropic.com >
2026-07-10 05:09:07 +00:00
Kaiqin Kong and SolitaryThinker
f037351146
[feat] Add Clean-history Teacher Forcing and Causal Consistency Distillation ( #1505 )
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Co-authored-by: SolitaryThinker <wlsaidhi@gmail.com >
2026-07-07 08:13:11 +00:00
William Lin
78d606a3a7
[feat]: make VSA tile cache configurable for training ( #1444 )
2026-06-28 02:18:31 -07:00
Junda Su and Peiyuan Zhang
5854aec2ce
[feat] Add Wan RL DiffusionNFT training ( #1450 )
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Co-authored-by: Peiyuan Zhang <a1286225768@gmail.com >
2026-06-11 21:18:59 -07:00
Mingjia Huo
63030cf6ec
[fix] Fix causal self-forcing attention settings ( #1355 )
2026-05-17 22:59:47 -07:00
Kaiqin Kong and mergify[bot]
773d44b875
[misc] Rename MatrixGame to MatrixGame2 ( #1357 )
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Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2026-05-17 22:57:03 -07:00
1df513922f
[feat] Add minimal LoRA finetuning support to the YAML training stack ( #1242 )
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Co-authored-by: alexzms <3036648523@qq.com >
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2026-05-17 14:49:13 -07:00
William Lin
c5088670c8
[misc]: empty __init__.py files with no logic ( #1346 )
2026-05-13 13:09:40 -07:00
d6dfe95466
[feat] FastVideo World Model Training ( #1179 )
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Co-authored-by: mignonjia <mhuo@ucsd.edu >
Co-authored-by: alexzms <3036648523@qq.com >
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2026-05-11 05:13:12 +00:00
alexzms
9a8bbe18fa
[bugfix]: fix SP deadlock in negative prompt encoding during training ( #1178 )
2026-04-28 01:06:49 +00:00
alexzms
d92858659d
[feat] Self-Forcing methods in refactored training infra ( #1164 )
2026-03-09 20:20:59 -07:00
1a383f3f66
[refactor] train v1 clean up
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Co-authored-by: alexzms <3036648523@qq.com >
Co-authored-by: Peiyuan Zhang <a1286225768@slurm-h200-204-215.slurm-compute.tenant-slurm.svc.cluster.local >
2026-03-09 18:58:56 -07:00
alexzms and Peiyuan Zhang
bc27a032c5
[feat] Refactor training framework into fastvideo/train ( #1159 )
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Co-authored-by: Peiyuan Zhang <a1286225768@gmail.com >
2026-03-09 15:16:42 -07:00
William Lin