5 people aaef49bfc6 [feat]: run FastH3 across two DGX Sparks with Ray sequence parallel (#1803) ...

Co-authored-by: Kyle <shh075@ucsd.edu>
Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
Co-authored-by: Satyam Srivastava <srivastavasatyam53@gmail.com>
Co-authored-by: Aryan Kumar <aryan5v@users.noreply.github.com>

2026-09-01 01:37:23 -07:00

..

test_cpu_sdpa.py

[perf] Add MiniMax H3 MLX VSA and SIMD attention (#1776)

2026-08-30 13:44:54 -07:00

test_mps_vsa_error.py

[feat]: Apple Silicon MLX runtime — INT8 Wan2.1 and Wan2.2 inference (#1638)

2026-08-18 15:08:00 -07:00

test_unified_memory_offload.py

[feat]: run FastH3 across two DGX Sparks with Ray sequence parallel (#1803)

2026-09-01 01:37:23 -07:00

test_unified_memory.py

[perf]: MiniMax H3 on GB10 - skip text encoder CPU offload on unified memory (5m49s to 30ms) (#1710)

2026-08-26 12:03:14 -07:00