3 people 3e87d6f4ae [feat] ROCm: route the video sparse attention backends to their Triton kernels (#1851) ...

Co-authored-by: SolitaryThinker <wlsaidhi@gmail.com>
Co-authored-by: Claude Opus 5.5 (1M context) <noreply@anthropic.com>

2026-10-07 02:32:27 -07:00

..

__init__.py

[bugfix] ROCm: detect the platform from a HIP torch build when amdsmi is unavailable (#1849)

2026-10-07 02:20:47 -07:00

cpu.py

[perf] Add MiniMax H3 MLX VSA and SIMD attention (#1776)

2026-08-30 13:44:54 -07:00

cuda.py

[feat] Add a typed environment-variable registry, policy doc, and contract test (#1896)

2026-09-29 12:50:45 -07:00

interface.py

[perf]: MiniMax H3 on GB10 - skip text encoder CPU offload on unified memory (5m49s to 30ms) (#1710)

2026-08-26 12:03:14 -07:00

mps.py

[perf]: MiniMax H3 on GB10 - skip text encoder CPU offload on unified memory (5m49s to 30ms) (#1710)

2026-08-26 12:03:14 -07:00

npu.py

[feat] Add a typed environment-variable registry, policy doc, and contract test (#1896)

2026-09-29 12:50:45 -07:00

rocm.py

[feat] ROCm: route the video sparse attention backends to their Triton kernels (#1851)

2026-10-07 02:32:27 -07:00