Aryan KumarandAryan Kumar 7c2b447264 [ci] Run single-GPU CI lanes on a DGX Spark runner; weekly full suite on main (#2007) ...

Co-authored-by: Aryan Kumar <aryan5v@users.noreply.github.com>

2026-10-22 13:44:55 -07:00

..

test_absmax_fp8.py

[misc] yapf pass under CI's interpreter (3.12) + pin hook language_version (#1702)

2026-08-08 22:24:17 -07:00

test_fp8_compute_gate.py

[bugfix] FP8: gate the ROCm _scaled_mm path on CDNA4 (gfx950) instead of the capability tuple (#1859)

2026-09-16 19:58:55 -07:00

test_fp8_quant_kernels.py

[perf] FP8: fuse the dynamic activation quantization into Triton kernels (#1861)

2026-10-07 03:20:04 -07:00

test_minimax_h3_modelopt_activation_scale.py

[feat]: FastH3 on single RTX GPUs (#1919)

2026-10-06 11:37:01 -07:00

test_minimax_h3_modelopt_nvfp4_converter.py

[feat]: FastH3 on single RTX GPUs (#1919)

2026-10-06 11:37:01 -07:00

test_mxfp8.py

[ci] Run single-GPU CI lanes on a DGX Spark runner; weekly full suite on main (#2007)

2026-10-22 13:44:55 -07:00

test_nvfp4_config.py

[feat]: FastH3 on single RTX GPUs (#1919)

2026-10-06 11:37:01 -07:00

test_nvfp4_dequant.py

[feat]: FastH3 on single RTX GPUs (#1919)

2026-10-06 11:37:01 -07:00

test_nvfp4_h3_dit_export.py

[feat]: FastH3 on single RTX GPUs (#1919)

2026-10-06 11:37:01 -07:00

test_nvfp4_ltx2_wiring.py

[misc] yapf pass under CI's interpreter (3.12) + pin hook language_version (#1702)

2026-08-08 22:24:17 -07:00

test_nvfp4_minimax_h3_wiring.py

[feat]: Community MiniMax-H3 LoRA loading with quantized side branch (#1973)

2026-10-19 14:29:23 -07:00

test_nvfp4_purge.py

[bugfix] Fix tests that fail on main: FastH3 Trim Spark audio, test isolation (#1957)

2026-10-18 16:07:59 -07:00

test_nvfp4_qat_receipt.py

[misc]: add LTX-2.3 fine-tuning example recipes (#1651)

2026-07-27 18:42:44 -07:00

test_nvfp4_row_split.py

[feat]: FastH3 OmniRef inference on consumer devices (RTX 5090 / PRO 6000 / DGX Spark / 4090) (#1980)

2026-10-19 14:57:36 -07:00

test_nvfp4_skip_blocks.py

[feat]: FastH3 OmniRef inference on consumer devices (RTX 5090 / PRO 6000 / DGX Spark / 4090) (#1980)

2026-10-19 14:57:36 -07:00

test_nvfp4_spark_fence.py

[ci] Run single-GPU CI lanes on a DGX Spark runner; weekly full suite on main (#2007)

2026-10-22 13:44:55 -07:00