Sweep all 296 v2 modules: simplify verbose docstrings/comments and remove 376 dangling "(design_vN §X)" citations to the now-deleted design docs (v2/README.md is the source of truth). Comment/docstring-only — AST-verified code-identical; the CPU suite holds at 237 passed / 5 pre-existing. Also applies yapf + ruff --fix auto-fixes (import ordering, forward-ref annotation de-quoting under `from __future__ import annotations`; behavior- neutral, suite-confirmed) and adds the legitimate domain terms mot/clen/te to the codespell ignore-list. Remaining ruff (24) + mypy (68 no-untyped-call) findings are pre-existing v2 debt, untouched here.
63 lines
2.9 KiB
Python
63 lines
2.9 KiB
Python
"""The batch-of-N interleave parity gate — required, not optional.
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Loop inversion's real hazard is cross-request state smearing under interleaving, which a
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batch-of-1 parity gate cannot detect. So this gate runs two or more concurrent requests
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interleaved at step granularity and requires bit-identical output versus running them serially.
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The gate is pure and duck-typed: it takes any engine exposing ``run_serial`` and ``run_interleaved``.
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"""
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from __future__ import annotations
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from typing import Any
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from v2.request.artifacts import (
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Output, )
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from v2.parity.ladder import ConsistencyLevel, Divergence, bit_identical
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def _artifact_payload(art: Any) -> Any:
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for attr in ("frames", "samples", "tensor", "latent", "token_ids", "text"):
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if hasattr(art, attr) and getattr(art, attr) is not None:
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return getattr(art, attr)
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return None
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def compare_outputs(serial: dict[str, Output], interleaved: dict[str, Output]) -> list[Divergence]:
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"""Bitwise-compare per-request outputs from serial vs interleaved runs."""
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divs: list[Divergence] = []
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if set(serial) != set(interleaved):
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divs.append(
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Divergence("request_set", ConsistencyLevel.C1, float("inf"), float("inf"),
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f"serial reqs {set(serial)} != interleaved {set(interleaved)}"))
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return divs
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for rid in sorted(serial):
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so, io = serial[rid], interleaved[rid]
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if set(so.artifacts) != set(io.artifacts):
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divs.append(
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Divergence(f"{rid}:artifacts", ConsistencyLevel.C1, float("inf"), float("inf"),
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f"artifact names differ: {set(so.artifacts)} vs {set(io.artifacts)}"))
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continue
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for name in sorted(so.artifacts):
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a, b = _artifact_payload(so.artifacts[name]), _artifact_payload(io.artifacts[name])
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if a is None and b is None:
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# both empty is NOT parity — a deferred/aborted request must not pass the gate vacuously
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divs.append(
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Divergence(
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f"{rid}:{name}", ConsistencyLevel.C1, float("inf"), float("inf"),
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"both serial and interleaved produced EMPTY output for a declared "
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"artifact (deferred/aborted?) — suspicious, not parity"))
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continue
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if not bit_identical(a, b):
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divs.append(
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Divergence(f"{rid}:{name}", ConsistencyLevel.C1, float("nan"), float("nan"),
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"serial vs interleaved output not bit-identical "
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"(cross-request state smearing!)"))
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return divs
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def assert_interleave_parity(engine: Any, requests: list[Any]) -> list[Divergence]:
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"""Drive ``engine`` both ways and return divergences (empty list == gate PASSES)."""
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serial = engine.run_serial(requests)
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interleaved = engine.run_interleaved(requests)
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return compare_outputs(serial, interleaved)
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