Peng Xiaoand肖鹏 a0bff12746 [bugfix] [dmd] Align backward simulation with dmd2 sample back (#744) ...

Co-authored-by: 肖鹏 <xiaopeng1@aishi.ai>

2025-08-20 22:25:33 -07:00

..

__init__.py

[Feature] Add DMD T2V training pipeline (#651)

2025-07-27 03:35:51 -04:00

activation_checkpoint.py

[Feature] Remove V1 folder (#642)

2025-07-24 22:43:12 -07:00

checkpointing_utils.py

[Feature] Remove V1 folder (#642)

2025-07-24 22:43:12 -07:00

distillation_pipeline.py

[bugfix] [dmd] Align backward simulation with dmd2 sample back (#744)

2025-08-20 22:25:33 -07:00

training_pipeline.py

Fix LoRA load from training checkpoint (#719)

2025-08-09 20:46:00 -05:00

training_utils.py

Fix LoRA load from training checkpoint (#719)

2025-08-09 20:46:00 -05:00

wan_distillation_pipeline.py

[Fix] training pipeline pin_cpu_memory issue (#692)

2025-08-07 02:31:20 -07:00

wan_i2v_distillation_pipeline.py

[bugfix] [distill] remove i2v validation schema import in distill (#728)

2025-08-09 20:47:42 -07:00

wan_i2v_training_pipeline.py

[Bugfix] Add i2v vae loading (#686)

2025-08-01 23:15:37 -04:00

wan_training_pipeline.py

[Fix] training pipeline pin_cpu_memory issue (#692)

2025-08-07 02:31:20 -07:00