Second step of the runtime simplification (after cost removal). Drop the
coordinated step-interleave scheduler + the interleave-parity gate; serving is
now pooled run-to-completion.
- Engine: remove run_interleaved + the WorkUnit/BatchScheduler imports; run /
run_serial drive each request to completion (tick/run_to_completion kept as the
per-request stepper).
- scheduler.py: remove BatchScheduler + WorkUnit + the batches metric; the
AdmissionController is now a pure refundable memory/OOM guard.
- AsyncEngine: bound concurrency with a serving pool (asyncio.Semaphore,
max_concurrent) — each request waits for a slot, then runs to completion.
- parity: remove assert_interleave_parity (the run_serial==run_interleaved gate);
rename interleave_gate.py -> compare.py (compare_outputs stays — bit-parity
between execution paths, e.g. disaggregated==inline).
- card specs: drop ParitySpec.interleave_required + LoopSpec.allows_interleaving;
stripped interleave_required from all cards.
- tests: delete the interleave-gate/parity tests; refocus the ones that exercised
real behavior (residual-skip, compare_outputs symmetric-empty).
- README: removed the design-doc references at the top; simplified the thesis /
scheduler (§6) / parity (§9) / package-layout / comparison sections to pooled
run-to-completion (no cost model, no interleave gate).
CPU mini: 143 passed / 2 skipped. Native omni port (P3) still to come. (pyproject
kernel hack excluded.)
SolitaryThinker
290795daf8