SolitaryThinker
4e331eb7ff
Mechanical conversion of every relative import under v2/ to an absolute v2.* path (from .x / ..x / ...x -> from v2.<pkg>.x) so imports are unambiguous, grep-able, and stable when code is copied/moved between entrypoints (VideoGenerator, CLI, server). Surgical prefix-only rewrite: only the 'from <dots><module>' prefix changed — import names, parentheses, multi-line formatting, comments, and ordering are byte-for-byte preserved (no collapsing, no reorder, no unrelated reformatting). - 471 imports across 125 files; v2/tests/ was already absolute (untouched). - Validated: all 125 files compile, every 'from v2.* import' target resolves to a real module/package, zero relative imports remain (full sweep), CPU mini suite green (202 passed, 2 skipped).
66 lines
3.1 KiB
Python
66 lines
3.1 KiB
Python
"""The batch-of-N interleave parity gate (design_v3 §9.3) — non-negotiable.
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> Loop inversion's real hazard is cross-request state smearing under interleaving — and a
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> batch-of-1 parity gate is structurally blind to it. So v3 makes a batch-of-N interleave
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> parity test a *required* gate: two (or more) concurrent requests, interleaved at step
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> granularity, must be bit-identical to the same requests run serially.
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This is the test the whole loop-inversion bet lives or dies on. The gate is pure and
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duck-typed: it takes any engine exposing ``run_serial`` and ``run_interleaved``.
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"""
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from __future__ import annotations
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from typing import Any
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from v2.request.artifacts import (
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AudioArtifact,
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LatentArtifact,
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Output,
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TensorArtifact,
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TextArtifact,
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VideoArtifact,
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)
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from v2.parity.ladder import ConsistencyLevel, Divergence, bit_identical
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def _artifact_payload(art: Any) -> Any:
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for attr in ("frames", "samples", "tensor", "latent", "token_ids", "text"):
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if hasattr(art, attr) and getattr(art, attr) is not None:
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return getattr(art, attr)
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return None
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def compare_outputs(serial: dict[str, Output], interleaved: dict[str, Output]) -> list[Divergence]:
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"""Bitwise-compare per-request outputs from serial vs interleaved runs."""
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divs: list[Divergence] = []
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if set(serial) != set(interleaved):
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divs.append(Divergence("request_set", ConsistencyLevel.C1, float("inf"), float("inf"),
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f"serial reqs {set(serial)} != interleaved {set(interleaved)}"))
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return divs
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for rid in sorted(serial):
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so, io = serial[rid], interleaved[rid]
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if set(so.artifacts) != set(io.artifacts):
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divs.append(Divergence(f"{rid}:artifacts", ConsistencyLevel.C1, float("inf"), float("inf"),
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f"artifact names differ: {set(so.artifacts)} vs {set(io.artifacts)}"))
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continue
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for name in sorted(so.artifacts):
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a, b = _artifact_payload(so.artifacts[name]), _artifact_payload(io.artifacts[name])
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if a is None and b is None:
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# both empty is NOT parity — a deferred/aborted request must not pass the gate vacuously
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divs.append(Divergence(f"{rid}:{name}", ConsistencyLevel.C1, float("inf"), float("inf"),
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"both serial and interleaved produced EMPTY output for a declared "
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"artifact (deferred/aborted?) — suspicious, not parity"))
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continue
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if not bit_identical(a, b):
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divs.append(Divergence(f"{rid}:{name}", ConsistencyLevel.C1, float("nan"), float("nan"),
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"serial vs interleaved output not bit-identical "
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"(cross-request state smearing!)"))
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return divs
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def assert_interleave_parity(engine: Any, requests: list[Any]) -> list[Divergence]:
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"""Drive ``engine`` both ways and return divergences (empty list == gate PASSES)."""
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serial = engine.run_serial(requests)
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interleaved = engine.run_interleaved(requests)
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return compare_outputs(serial, interleaved)
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