 rlsu9
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58440f43de
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Merge branch 'main' of https://github.com/jzhang38/FastVideo-OSP into peiyuan
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2024-12-01 05:26:04 +04:00 |
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rlsu9
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c8238e1f7b
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typo
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2024-12-01 05:25:23 +04:00 |
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Zhang Peiyuan
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5ff08541f6
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[Debug] Typo (#65)
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2024-11-30 17:14:14 -08:00 |
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rlsu9
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f771899001
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update
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2024-12-01 05:13:51 +04:00 |
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rlsu9
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c609c28e63
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update
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2024-12-01 05:04:33 +04:00 |
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rlsu9
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c19f72f722
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typo
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2024-12-01 04:44:42 +04:00 |
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rlsu9
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43b4778474
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Merge branch 'main' of https://github.com/jzhang38/FastVideo-OSP into peiyuan
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2024-12-01 04:44:29 +04:00 |
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Zhang Peiyuan
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08f5489406
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[Feat & Debug] fix uncond; multi guidance validaiton; multiphase schedule; linear range (#64)
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2024-11-30 16:43:24 -08:00 |
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rlsu9
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7e6e52e02a
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update
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2024-12-01 04:39:44 +04:00 |
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rlsu9
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e4114d8fd4
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merge main
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2024-12-01 04:35:01 +04:00 |
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rlsu9
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a19ed188c8
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add script
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2024-12-01 04:32:22 +04:00 |
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rlsu9
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6d3a71b681
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linear range; fix uncond; multi guidance validation
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2024-12-01 04:31:53 +04:00 |
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Zhang Peiyuan
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81103cd48d
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[Feat] EMA Distill; Distributed validation (#63)
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2024-11-29 21:46:40 -08:00 |
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rlsu9
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a3d4a1cef4
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add gupload
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2024-11-30 09:41:37 +04:00 |
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rlsu9
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954dc8e35c
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distributed validation
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2024-11-30 09:39:00 +04:00 |
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rlsu9
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278e8bb8f3
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Merge branch 'main' into peiyuan
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2024-11-30 05:28:37 +04:00 |
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rlsu9
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b378896b82
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readme
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2024-11-30 05:28:02 +04:00 |
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rlsu9
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1d2a7f233c
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distributed validation
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2024-11-30 05:24:05 +04:00 |
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rlsu9
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b4aed1721f
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add aws efo env
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2024-11-30 03:44:43 +04:00 |
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rlsu9
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3447ded21b
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revert to sp=4, sp bs=2, full shard
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2024-11-30 03:43:39 +04:00 |
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rlsu9
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0c01223d3d
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update script; no sp
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2024-11-30 02:51:22 +04:00 |
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rlsu9
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f8089afbf1
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ema
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2024-11-30 02:44:36 +04:00 |
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rlsu9
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2b0c1e66cb
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update env
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2024-11-29 22:52:19 +04:00 |
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rlsu9
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79e7dac0ac
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ok
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2024-11-29 21:50:49 +04:00 |
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rlsu9
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2b3f3cddd4
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remove hardcode
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2024-11-29 19:35:30 +04:00 |
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rlsu9
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064195363c
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remove harcode
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2024-11-29 19:34:02 +04:00 |
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rlsu9
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ed1e17f37f
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add ema transformer
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2024-11-29 11:42:17 +04:00 |
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rlsu9
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e32d137aec
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add ema_transform
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2024-11-29 11:11:46 +04:00 |
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rlsu9
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62a5530c21
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add
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2024-11-29 11:08:32 +04:00 |
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rlsu9
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b3be22e1e2
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add upload command
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2024-11-29 09:44:13 +04:00 |
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rlsu9
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7156b8d7d5
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typo
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2024-11-29 09:12:22 +04:00 |
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Zhang Peiyuan
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6dd7980ec2
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[Feat] Refactor GAN; State saving & Resume; Experiments script (#59)
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2024-11-28 21:09:31 -08:00 |
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Zhang Peiyuan
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b3c54b9e5b
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[Feat] Training precision (#57)
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2024-11-27 16:25:07 -08:00 |
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Zhang Peiyuan
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333488ac09
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[Feat][Debug] linear quadratic distill; HF precision bug (#56)
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2024-11-27 15:13:20 -08:00 |
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Zhang Peiyuan
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c7526707cc
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[Fix] Squeeze bug (#55)
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2024-11-26 13:29:03 -08:00 |
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Zhang Peiyuan
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a0ffbe2927
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[Feat] PCM Distill; Refactor FM logit to be compatible with all SD3/Flux scheduler. (#54)
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2024-11-26 12:26:24 -08:00 |
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rlsu9andRunlong
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faef037f2e
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[feat]: Add batchy data preprocess (#53)
Co-authored-by:Runlong <rlsu9@ucsd.edu>
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2024-11-25 21:52:36 -08:00 |
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rlsu9andrunlong
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9c45a15f53
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[feat]: Add Image-Video Mixture training to main repo (#50)
Co-authored-by: runlong <r3su@ucsd.edu>
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2024-11-24 14:36:45 -08:00 |
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Zhang Peiyuan
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e6ff7ae2a3
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Resolve config bug and seed (#51)
Co-authored-by: Peiyuan Zhang <a1286225768@gmail.com>
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2024-11-15 20:29:48 -08:00 |
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Zhang Peiyuan
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897afb8b94
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Add LADD (#45)
Co-authored-by: Peiyuan Zhang <a1286225768@gmail.com>
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2024-11-15 19:28:41 -08:00 |
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f8178a5a14
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add lr scheduler; precision bug fix; add naive dataloader resume (#49)
Co-authored-by: Peiyuan Zhang <a1286225768@gmail.com>
Co-authored-by: Yongqi Chen <yongqich@gl1712.arc-ts.umich.edu>
Co-authored-by: Yongqi Chen <yongqich@gl-login3.arc-ts.umich.edu>
Co-authored-by: Yongqi Chen <yongqich@gl-login1.arc-ts.umich.edu>
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2024-11-14 19:57:38 -08:00 |
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4c76b3cc7a
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[Feat] Lora resume (#48)
Co-authored-by: Peiyuan Zhang <a1286225768@gmail.com>
Co-authored-by: Yongqi Chen <yongqich@gl1712.arc-ts.umich.edu>
Co-authored-by: Yongqi Chen <yongqich@gl-login3.arc-ts.umich.edu>
Co-authored-by: Yongqi Chen <yongqich@gl-login1.arc-ts.umich.edu>
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2024-11-12 22:30:58 -08:00 |
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3e0e8cf534
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Add lora (#47)
Co-authored-by: Yongqi Chen <144848849+BrianChen1129@users.noreply.github.com>
Co-authored-by: Yongqi Chen <yongqich@gl1712.arc-ts.umich.edu>
Co-authored-by: Yongqi Chen <yongqich@gl-login3.arc-ts.umich.edu>
Co-authored-by: Yongqi Chen <yongqich@gl-login1.arc-ts.umich.edu>
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2024-11-11 13:12:14 -08:00 |
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Zhang Peiyuan
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635fb2350d
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[Refactor] Switch to FSDP (#42)
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2024-11-09 15:46:25 -08:00 |
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Zhang Peiyuan
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a52f29374c
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No checkout mochi
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2024-11-07 20:49:14 -08:00 |
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rlsu9andhaoanyscale
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31827c9e0a
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[feat]: Add adaptive fps dataloader and remove redundant code (#41)
Co-authored-by: haoanyscale <c-hao.zhang@anyscale.com>
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2024-11-06 19:52:48 -08:00 |
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rlsu9andhaoanyscale
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74688e56b5
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[feat]: Add vae encoder embedded generator to main (#30)
Co-authored-by: haoanyscale <c-hao.zhang@anyscale.com>
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2024-11-06 11:58:15 -08:00 |
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Zhang Peiyuan
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e56b2ae0c4
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Add validation logging with SP (#36)
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2024-11-05 14:46:20 -08:00 |
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Zhang Peiyuan
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6c6d4b34e7
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[Feat] Sequence Parallel (#31)
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2024-11-05 08:13:01 -08:00 |
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Zhang Peiyuan
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93d6ee49ba
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Merge pull request #25 from jzhang38/peiyuan
SP inference and Overfit training done.
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2024-11-01 17:27:30 -07:00 |
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